1. Field of the Invention
The present invention relates to a semiconductor device composing a semiconductor integrated circuit used for controlling a power source voltage of a portable device or the like and a manufacturing method therefor.
2. Description of the Related Art
FIG. 2 is a schematic cross sectional view of a conventional semiconductor device. This device has a complementary MOS (hereinafter referred to as a CMOS) structure composed of an N-channel MOS (hereinafter referred to as an NMOS) transistor which is formed in a P-type semiconductor substrate and in which a gate electrode is made of N+-type polycrystalline silicon and a P-channel MOS (hereinafter referred to as a PMOS) transistor which is formed in an N-well region and in which a gate electrode is made of N+-type polycrystalline silicon. Generally, a semiconductor integrated circuit device is composed of these MOSFETs.
With respect to the semiconductor device having the above conventional structure, in the case of an enhancement type NMOS (hereinafter referred to as an E-type NMOS) transistor having a standard threshold voltage of about 0.7 V, the gate electrode is made of polycrystalline silicon having an N+-type as a conductivity type. Thus, from a relationship of work functions between the gate electrode and a semiconductor substrate, the channel is a surface channel formed in the surface of the semiconductor substrate. On the other hand, in the case of an enhancement type PMOS (hereinafter referred to as an E-type PMOS) transistor having a standard threshold voltage of about −0.7 V, from a relationship of work functions between the gate electrode made of N+-type polycrystalline silicon and an N-well, the channel becomes a buried channel formed somewhat inside the semiconductor substrate rather than the surface of the semiconductor substrate.
In order to realize low voltage operation, when a threshold voltage is set to be, for example, −0.5 V or more in the buried channel E-type PMOS transistor, a subthreshold characteristic as one index for low voltage operation of the MOS transistor is extremely deteriorated. Thus, a leak current at an off state of the PMOS transistor is increased. As a result, since a consumption current during standby of the semiconductor device is markedly increased, there is a problem in that an application to portable devices represented by a mobile telephone and a personal digital assistant which are said to increase demand in recent years and to further expand the market in the future is difficult. Also, when the channel length of the PMOS transistor is increased to reduce the leak current, drive power of the PMOS transistor is decreased. Thus, in order to supplement the reduced drive power, the channel width of the PMOS transistor is increased by necessity. Therefore, an increase in a chip area and an increase in a cost due to that are caused. This is a serious problem particularly in a semiconductor integrated circuit having the PMOS transistor as an output driver.
On the other hand, as a technical method of making compatibility of low voltage operation and a low consumption current as the above objects, as shown in FIGS. 3 and 4, a so-called homopolar gate technique in which a conductivity type of the gate electrode of an NMOS transistor is made to be an N-type and a conductivity type of the gate electrode of a PMOS transistor is made to be a P-type is generally known. In this case, both an E-type NMOS transistor and an E-type PMOS transistor are surface channel MOS transistors. Thus, even when a threshold voltage is reduced, extreme deterioration of a subthreshold coefficient is not reached and both low voltage operation and low consumption power are possible.
However, there are the following problems in cost and characteristic. That is, with respect to a homopolar gate CMOS structure, the gates in both an NMOS transistor and a PMOS transistor are formed to be different polarities in manufacturing steps. Thus, as compared with a CMOS structure having a gate electrode made of only an N+-polycrystalline silicon monopole, the number of steps is increased and increases in a manufacturing cost and a manufacturing period are caused. Further, with respect to an inverter circuit as a most fundamental circuit element, generally, in order to improve area efficiency, the layout for the gates of the NMOS transistor and the PMOS transistor is made such that a connection through metal is avoided and a piece of polycrystalline silicon which is two-dimensionally continued from the NMOS transistor to the PMOS transistor or a polycide structure composed of a laminate of polycrystalline silicon and high melting metallic silicide is used. However, when the gate is made of polycrystalline silicon as a single layer as shown in FIG. 3, it is impractical because of a high impedance of a PN junction in the polycrystalline silicon. Also, when the gate is made of the polycide structure as shown in FIG. 4, an N-type impurity and a P-type impurity each are diffused respectively to gate electrodes having an inverse conductivity type through the high melting metallic silicide at high speed during thermal treatment in the manufacturing steps. As a result, a work function is changed and a threshold voltage is unstable.